As back end of line (BEOL) processes are scaled down, filling copper dual damascene trenches becomes more difficult. A known approach involves using a linear material such as ruthenium (Ru) and cobalt (Co) to facilitate Cu filling. In particular, a cavity is formed in an ultra-low k dielectric (ULK) 101, e.g., a dielectric having a dielectric constant less than 3, as depicted in FIG. 1A. Next, a tantalum nitride/tantalum (TaN/Ta) layer 121 is conformally formed in the cavity and over the ULK 101 to a thickness of 1 nm to 10 nm, as illustrated in FIG. 1B. Adverting to FIG. 1C, a Ru layer 131 is conformally formed over the TaN/Ta layer 121 to a thickness of 0.5 nm to 5 nm. Thereafter, Cu 141 is deposited over the Ru layer 131, filling the cavity, as depicted in FIG. 1D. Adverting to FIG. 1E, the Cu 141, the Ru layer 131, and the TaN/Ta layer 121 are planarized by chemical mechanical polishing (CMP). However, because the polishing rate of the Ru layer 131, e.g., 5 nm/min, is much slower than the polishing rate of the TaN/Ta layer 121, e.g., 50-70 nm/min, the TaN/Ta layer 121 is degraded in a number of places along the trench leaving spaces 143 between the ULK 101 and the Ru layer 131. Next, a dielectric cap 151 is deposited over the TaN/Ta layer 121, the spaces 143, the Ru layer 131, and the Cu 141, as illustrated in FIG. 1F. Since a space remains at 143, device reliability is reduced by issues such as barrier and/or time-dependent dielectric breakdown (TDDB) degradation.
A need therefore exists for methodology enabling formation of an improved Cu barrier, and the resulting device.